520: Advanced Computer Architecture (Fall 2008)
|| Tu, Th 12:15 P.M. - 1:30 P.M. BYAC 260
|| Sandeep Gupta
||M, W 3:30 P.M. - 5:00 P.M.
|TA Office Hour
Goal and Topics
Computer architecture. Performance versus cost tradeoffs. Instruction set design. Basic processor
implementation and pipelining. Instruction-level parallelism and its exploitation.
Multiprocessors and thread-level parallelism. Memory hierarchy design.
Storage systems. (more course information
The course topics will be covered through lectures and student paper presentations.
At the beginning of the semester, students will be given a list of papers organized by topics and are
required to do the following:
Each student will choose one paper that he or she is going to present to the class.
The TA will announce the presentation schedule later.
There will be one or two paper presentations in each class.
A presenter is required to submit the presentation slides a day before the presentation.
- Critique: For each paper, there will be 3 designated critics.
A critic is required to submit his or her critique of the presentation as well as the paper.
The latter will be posted on the course web.
- In-class and online discussion:
Students can ask questions during presentation.
Besides, the class will also discuss the paper on a
Students will be evaluated based on their participation in the discussions.
There will be a student designated to summarize the online discussion of each paper.
The summary will be posted on the course web as well.
To sum up, each student will do at least 1 paper presentation, 3 critiques, 1 paper summary,
and online and inclass paper discussion. The performance and participation in each process of
paper study will constitute a major portion of the class grade.
Another major portion of the class grade will be based on the term project.
Each student will conduct in-depth research on a computer architecture topic of his/her
choice for the term project.
- Phase I:
In Phase I of the research the student will choose a topic to work on in consultation
with the instructor and submit a written report per the
- Phase II:
In Phase II of the research the student will thoroughly survey the selected topic,
define a research problem related to the chosen topic, propose a solution and submit a
written report per the requirments.
- Phase III:
In Phase III, the student evaluates the solution using mathematical analysis,
simulation, and/or implementation. A student is required to make an oral presentation on
his/her accomplishments for the term project in either one of the last two classes and
submit a written report at the time of final exam. More details on term projects will
be discussed in class.
There will be quizzes, homeworks and a final exam based on the course material covered in the class.
The following grading rubric will be used to evaluate all the submitted material and performance tasks:
A+: Student shows superior understanding of purpose and significance of the problem; is able to identify
related problems; has solved the problem using novel approach and insight.
A: Student shows good understanding of purpose and significance of the problem; is able to identify related problems;
has solved the problem displaying some degree of insight.
B: Student can solve the problem with some sophistication but is unable to judge its importance.
C: Student lacks understanding of how to approach the problem or proposes very naive solutions for the problem.
The final letter grade will be assigned based on weighted average of the grades obtained in the following categories:
Notice: the above description is not finalized and subject to change. Student should check back this
page on a regular basis.
| phase I
| phase II
| phase III
|Quiz, homwork, exam
||Computer architecture introduction
||Computer architecture introduction
Topics covered so far,
||Power Issues and Dependability
Quiz 1 grades
||Power Issues and Case Studies
(1) Cost-effective Parallel Computing,
(2) Validity of the Single Processor Approach,
(3) Reevaluating Amdhal's Law,
(4) Amdhal's Law in Multicore Era
||Introduction to Multicore Perspecitve
||class notes, Quiz 2, Quiz 2 grades
(1) Thousand Core Chips - A Technology Perspective
(2) Design Challenges of Technology Scaling
(1) Techniques for Multicore Thermal Management: Classification and New Exploration
(2) Understanding the Thermal Implications of Multicore Architectures
(3) Dynamic Thermal Management for High-Performance Microprocessors
||Assignment 1, Matlab Code for FCFS First Fit
(1) Ensemble-level Power manage
ment for Data Blade Server
(2) Power and Energy Management for Server Systems, published in Computer
Thermal-Aware Task Scheduling for Homogeneous, High Performance Computing Data Centers: A Cyber-Physical Approach
||class note, Assignment Doubts
||Cache Design for Multicores
(1) Exploring the Cache Design Space for Large Scale CMPs
(2) Cooperative Caching for Chip Multiprocessors
(3) Virtual Hierarchies to Support Server Consolidation
||Case Study: Bus-based Multiprocessor
||class notes, slides
||Directory-based Cache Coherency Protocol
||class notes, Quiz 3 Grades
(1) Xen and the Art of Virtualization
(2) Intel Virtualization Technology
||Assignment 1 grades
||Basics of Pipelining
||Multiprocessor Memory Management
||Sequential Hardware Prefetching in Shared-Memory Multiprocessors by Dahlgren, Dubois and Stenstrom, presented by, Srivatsan Chellappa (ppt),Critique 1,Critique 2, Critique 3, Summary
||Multiprocessor Memory Management
||Using Prediction to Accelerate Coherence Protocols by Mukherjee and Hill presented by ,Naresh Sukumar (ppt),Critique 1,Critique 2, Critique 3, Summary
Optimizing Replication, Communication, and Capacity Allocation in CMPs by Chishti, Powell and Vijaykumar presented by ,Siddhesh Mhambrey (ppt),Critique 1,Critique 2, Critique 3, Summary
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors by Speight, Shafi, Zhang and Rajamony presented by ,Aniket Bharadswadkar (ppt), Critique 1,Critique 2, Critique 3, Summary
||Power Aware Cache design ann Memory Ordering
||Power Savings in Embedded Processors through Decode Filter Cache by Weiyu Tang, Rajesh Gupta and Alexandru Nicolau presented by , Fei Hong (ppt), Critique 1,Critique 2, Critique 3, Summary
Conditional Memory Ordering by Christoph von Praun, Harold W. Cain, Jong-Deok Choi, Kyung Dong Ryu presented by , Renwei Yu (ppt), Critique 1,Critique 2, Critique 3, Summary
||Hyperthreading and synchronization issues
||Facilitating Efficient Synchronization of Asymmetric Threads on Hyper-Threaded Processors by Nikos Anastopoulos and Nectarios Koziris presented by James Coleman (ppt), Critique 1,Critique 2, Critique 3, Summary
Hyperthreading Technology in the Netburst Microarchitecture by David Koufaty Deborah T. Marr Intel presented by Nicolas Tjioe (ppt),Critique 1,Critique 2, Critique 3, Summary
||Proactive Fault Tolerance for HPC with Xen Virtualization by Arun Babu Nagarajan, Frank Mueller, Christian Engelmann , Stephen L. Scott presented by Stephen Orchowski (ppt), Critique 1,Critique 2, Critique 3, Summary
Multiplex: Unifying Conventional and Speculative Thread-Level Parallelism on a Chip Multiprocessor by Seon Wook Kim, Chong-Liang Ooi, Il Park, Rudolf Eigenmann, Babak Falsafi, and T. N. Vijaykumar presented by Ashok Venkatesan (ppt), Critique 1,Critique 2, Critique 3, Summary
Enforcing Performance Isolation Across Virtual Machines in Xen by Diwaker Gupta, Ludmila Cherkasova, Rob Gardner, and Amin Vahdat presented by Venkatraghavan Ramesh (ppt), Critique 1,Critique 2, Critique 3, Summary
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design by Wei-fen Lin, Steven K. Reinhardt and Doug Burger presented by Pravin Dalale (ppt), Critique 1,Critique 2, Critique 3, Summary
||Drowsy Caches: Simple Techniques for Reducing Leakage Power by Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge presented by Harshit Khanna (ppt), Critique 1,Critique 2, Critique 3, Summary
|| slides, Project Presentation Schedule
Instruction Level Power Estimation:
Microarchitecture Level Power Estimation:
Fuel and Solar Cells:
POLICY ON CHEATING
Any incidence of cheating in this class will be severely dealt with. This applies to homework assignments, programming assignments, quizzes and tests. The minimum penalty for cheating will be that the student will not obtain any credit for that particular assignment. (This means that if in a test and/or assignment a student is found have cheated, he/she will obtain zero in that test and/or assignment.) For the homework and the programming assignments students may discuss the problems with others, but one is expected to turn in the results of one's own effort (not the results of a friend's efforts). One tends to get very suspicious if two identically wrong results show up in the homework assignment and/or tests. The names of the offenders will be maintained in the departmental files. The repeat offenders may be debarred from the University.
Refer to Student Academic Integrity Policy for more information.