CSE 520: Advanced Computer Architecture (Fall 2007)

Lecture Tu, Th 3:15 P.M. - 4:30 P.M. BYAC 190
Line No 84994
Instructor Sandeep Gupta
Office BY522
Email Sandeep.Gupta@asu.edu
Office Hours Tu, Th 4:30 P.M. - 6:00 P.M.
TA Guofeng Deng (Guofeng.Deng@asu.edu)
TA Office BY517AE
TA Office Hour W 2 P.M. - 5 P.M.


CONTENTS

ANNOUNCEMENT


COURSE DESCRIPTION

Goal and Topics

Computer architecture. Performance versus cost tradeoffs. Instruction set design. Basic processor implementation and pipelining. Instruction-level parallelism and its exploitation. Multiprocessors and thread-level parallelism. Memory hierarchy design. Storage systems. (more course information)

Course Format

The course topics will be covered through lectures and student paper presentations. At the beginning of the semester, students will be given a list of papers organized by topics and are required to do the following:

  • Presentation: Each student will choose one paper that he or she is going to present to the class. The TA will announce the presentation schedule later. There will be one or two paper presentations in each class. A presenter is required to submit the presentation slides a day before the presentation.
  • Critique: For each paper, there will be 3 designated critics. A critic is required to submit his or her critique of the presentation as well as the paper. The latter will be posted on the course web.
  • In-class and online discussion: Students can ask questions during presentation. Besides, the class will also discuss the paper on a class blog. Students will be evaluated based on their participation in the discussions.
  • Summary: There will be a student designated to summarize the online discussion of each paper. The summary will be posted on the course web as well.

To sum up, each student will do at least 1 paper presentation, 3 critiques, 1 paper summary, and online and inclass paper discussion. The performance and participation in each process of paper study will constitute a major portion of the class grade.

Another major portion of the class grade will be based on the term project. Each student will conduct in-depth research on a computer architecture topic of his/her choice for the term project.

  • Phase I: In Phase I of the research the student will choose a topic to work on in consultation with the instructor and submit a written report per the requirements.
  • Phase II: In Phase II of the research the student will thoroughly survey the selected topic, define a research problem related to the chosen topic, propose a solution and submit a written report per the requirments.
  • Phase III: In Phase III, the student evaluates the solution using mathematical analysis, simulation, and/or implementation. A student is required to make an oral presentation on his/her accomplishments for the term project in either one of the last two classes and submit a written report at the time of final exam. More details on term projects will be discussed in class.

There will be quizzes, homeworks and a final exam based on the course material covered in the class.

Grading

The following grading rubric will be used to evaluate all the submitted material and performance tasks:
A+: Student shows superior understanding of purpose and significance of the problem; is able to identify related problems; has solved the problem using novel approach and insight.
A: Student shows good understanding of purpose and significance of the problem; is able to identify related problems; has solved the problem displaying some degree of insight.
B: Student can solve the problem with some sophistication but is unable to judge its importance.
C: Student lacks understanding of how to approach the problem or proposes very naive solutions for the problem.

The final letter grade will be assigned based on weighted average of the grades obtained in the following categories:
Paper Study 40%
     presentation 10%
     critiques 10%
     summary 10%
     discussion 10%
Project 30%
     phase I 10%
     phase II 10%
     phase III 10%
Quiz, homwork, exam 30%


Notice: the above description is not finalized and subject to change. Student should check back this page on a regular basis.



ASSIGNMENTS

Assignment Points Date Assigned Due Date Files
Homework
    #1 100 Sun 09/16/2007 Tue 09/25/2007 HW1, Sample solution to book case studies
    PA#1 100 Thu 09/27/2007 Thu 10/18/2007 PA1, test cases: in_1, out_1, in_2, out_2, in_3, out_3, in_4, out_4, in_5, out_5
    PA#2 100 Thu 10/25/2007 Tue 11/20/2007 PA2
Quiz
Project
    proposal and presentation paper selection 9/25/2007 10/16/2007
    phase II report 10/30/2007 11/06/2007
    phase III report 11/08/2007 12/04/2007
Mid-term 50 Sat 10/06/2007 Tue 10/16/2007 midterm, Tullsen's paper
Final exam 100 Thu 12/06/2007 2:40-4:30PM, Tuesday, Dec 11st final, Ipek's paper, Herlihy's paper, Fan's paper


SCORES

LECTURE NOTES

Week Class # Date Topics Materials
1 1 08/21 Introduction slides
2 08/23 Computer architecture introduction slides, The ComingWave of Multithreaded Chip Multiprocessors
2 3 08/28 Role of performance and tracking technology slides
4 08/30 Quantifying Cost, Energy-Consumption, Performance, and Dependability slides, semiconductors
3 5 09/04 Thermal-aware Issues in Computers slides
6 09/06 Quiz discussion
4 7 09/11 Performance optimization of multi-core processors under thermal constraints slides, references: multi-core architecture overview, dynamic thermal management, thermal management in multi-core architecture
8 09/13 Cell processor, parallel architecture intro to cell processor, cell processor - to-do for academia, cell process and parallel programming
5 9 09/18 Explore multicore-based architectures for mobile edge computing device slides
10 09/20 Datacenter basics and Fulton HPC visiting Fulton HPC
6 11 09/25 High-performance computing slides
12 09/27 Clusters and MPI, programming assignment: game of life slides
7 13 10/2 SMP-cache coherence slides
14 10/04 Multiprocessor and memory coherence slides
8 15 10/09 Midterm midterm, Tullsen's paper
16 10/11 Midterm midterm, Tullsen's paper
9 17 10/16 Proposal one-on-one
18 10/18 Midterm discussion
10 19 10/23 PS3 cell tutorial slides, cell reference: cell user guide, SPE library, SIMD math library, performance analysis, user's guide, cell broadband engine programming tutorial
20 10/25 PS3 cell tutorial, PA2 assigned
11 21 10/30 register file power reduction by Saleel, Pradnyesh Saleel, Pradnyesh
22 11/01 Speculative multithreading on SMP, implicitly-multithreaded processors Sugavaneswaran, Ashay
12 23 11/06 Tomasulo's algorithm, decompression architecture for low power embedded systems Tomasulo slides, Yi-Hsin
24 11/08 Microarchitectural techniques for power gating of functional units, HyperTransport Technology I/O Link Sai Raghunath, Michael
13 25 11/13 Generating FPGA-accelerated DFT libraries, Optimizing the fast Fourier transform on a multi-core architecture Chi Li, Tao
26 11/15 Speed Scaling to Manage Energy and Temperature, An Analysis of Efficient Multi-Core Global Power Management Policies Ayan, Jun
14 27 11/20 P4 micro-architecture, The potential of the cell processor for scientific computing David, Aarul
15 28 11/27 Limits of Instruction-Level Parallelism, Exploring Design space of future CMPs, Hybrid multi-core architecture for boosting single-threaded performance Robert, Sushma, Peyman
29 11/29 project presentations schedule
16 30 12/04 project presentations schedule


REFERENCE



READING LIST

    ILP:     P4:     SMT:     MP:     Itanium:     Itanium:     Instruction Level Power Estimation:     Microarchitecture Level Power Estimation:     Battery Modeling:     Throttling:     Processor Pipeline:     Gating:     Register File:     Chip Multiprocessors:     Fuel and Solar Cells:     Flash Memory:     Transactional Memory:
  • TBD


POLICY ON CHEATING

Any incidence of cheating in this class will be severely dealt with. This applies to homework assignments, programming assignments, quizzes and tests. The minimum penalty for cheating will be that the student will not obtain any credit for that particular assignment. (This means that if in a test and/or assignment a student is found have cheated, he/she will obtain zero in that test and/or assignment.) For the homework and the programming assignments students may discuss the problems with others, but one is expected to turn in the results of one's own effort (not the results of a friend's efforts). One tends to get very suspicious if two identically wrong results show up in the homework assignment and/or tests. The names of the offenders will be maintained in the departmental files. The repeat offenders may be debarred from the University.

Refer to Student Academic Integrity Policy for more information.











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